1. Field of the Invention
This invention relates generally to data collection terminals. This invention relates particularly to apparatus for processing device interrupt signals including such devices as communication controllers.
2. Description of the Prior Art
A data collection terminal is made up of a number of peripheral devices and a microprocessor, all coupled to a common bus. When a peripheral device requests attention, it sends an interrupt signal on the bus to the microprocessor. In the prior art system, a central processor would poll the devices to determine which device interrupted. The central processor would then process the interrupt and generate a unique interrupt vector address on the bus. This required the central processor to utilize hardware and firmware to poll all the devices in the subsystem, prioritize those devices with active interrupts and generate the unique interrupt vectored address to enter into the firmware interrupt service routine.
There are various other types of interrupt processing systems in the prior art which are coupled to provide interrupt service in response to an interrupt signal received from any one of a number of sources such as peripherals connected to an input/output bus. Typically, the procedure followed for servicing interrupts from such peripherals first requires identifying the interrupting peripherals, next requesting the status of the peripheral, and then updating the status. This procedure is relatively slow and, in certain types of systems where interrupt routines are executed frequently, the acknowledge routine time may pose serious speed restraints on the total system. In one such interrupt system, as indicated in U.S. Pat. No. 3,881,174, the interrupt processing apparatus includes a computer which allows a peripheral, upon receiving an acknowledgement from a computer of an interrupt request which the peripheral previously generated, to simultaneously provide the computer with its address and status. This shortens the time required for processing the interrupt routine.
U.S. Pat. No. 4,030,075 describes a data processing system having a distributed priority network. This priority network is coupled with each of the units and indicates which is the highest priority unit requesting to transfer information over the bus. The priority network includes a priority bus with the units coupled closest to one end of the bus having a highest priority and units coupled at the other end of the bus having a lowest priority. All of the above systems have the disadvantage of having considerable hardware and time-consuming cycles to perform the connection to the bus.
The Honeywell 7760 display system is a central processor subsystem which controls a fixed number of peripheral subsystems. The 7760 is described in the "VIP 7760 Subsystem User's Reference Manual", Order No. AT45, Rev. 0, May 1978.
Each peripheral subsystem sends a unique request for an interrupt signal to the central processor subsystem which makes the highest priority peripheral subsystem operative in the display system. The number of peripheral subsystems in the display system is limited to the throughput capability of the central processor subsystem. The interrupt and priority apparatus in the display system can readily process interrupts from the maximum number of peripheral subsystems.
U.S. Pat. No. 4,240,140 describes priority interrupt apparatus for generating vectored addresses which does not have the versatility of the instant invention.
The Intel 8259A Programmable Interrupt Controller provides for more efficient interrupt operation by providing the capability of being used as a master and a slave, whereby readily handling up to 64 vectored priority interrupts. The Intel 8259A controller is described in the "Component Data Catalog 1981" published by Intel Corporation, 3065 Bowers Avenue, Santa Clara, Calif. 95051.
However, the prior art still limits the throughput of such proposal devices such as document handlers and communication cardholders such as universal synchronous asynchronous remote transmit controllers.